Introducing the multilevel modulation technology and the OFDM (Orthogonal Frequency Division Multiplexing) technology has recently been examined to further increase the speed and capacity of optical communication systems. As the result of the approach, application of the digital signal processing technologies to an optical transceiver is proving to be effective. A digital-to-analog converter DAC serving as an analog front-end circuit is indispensable on the transmitter side of such an optical transceiver. The digital-to-analog converter DAC is required to operate at a high speed of several ten GS/s.
As digital-to-analog converters DACs excellent in the high-speed operation, current-steering (current addition) digital-to-analog converters DACs as shown in FIGS. 24 and 25 are known well. The digital-to-analog converters DACs shown in FIGS. 24 and 25 are described even in books related to data converters such as non-patent reference 1: Behzad Razavi, “PRINCIPLES OF DATA CONVERSION SYSTEM DESIGN”, Chapter 5 “Current-Steering Architectures” and non-patent reference 2: B. Jalali et al, “InP HBTs: Growth, Processing and Applications”, Chapter 9 “Digital-To-Analog Converters”.
FIG. 24 is a block diagram showing an example of the circuit arrangement of a conventional current-steering (current addition) digital-to-analog converter DAC. In this example, the digital-to-analog converter DAC includes N current-switching cells. N currents having the same current value are weighted and added using a binary-weighted load resistor network (resistor ladder network) including a plurality of resistors formed in a ladder with resistance values R and 2R in accordance with the digital input signal bits of an N-bit binary code and thus converted into an analog output signal Vout and output.
That is, the digital-to-analog converter in FIG. 24 includes N current-switching cells CS10, CS1, CS2, . . . , and CSN-1, and more specifically, includes N D flip-flops (D-FF: circuits having a latch function) D-FF0, D-FF1, D-FF2, . . . , and D-FFN-1 which temporarily latch N digital input signal bits D0 (LSB side), D1, D2, . . . , and DN-1 (MSB side) and output the signal bits retimed by a clock signal CLK, respectively, N current sources which flow N currents having the same current value (I) to the binary-weighted load resistor network (resistor ladder network) including a plurality of resistors formed in a ladder with resistance values R and 2R, and switches S0, S1, S2, . . . , and SN-1 to be on/off-controlled based on the values of the digital input signal bits D0, D1, D2, . . . , and DN-1, respectively. Note that symbol VCC denotes a power supply configured to drive the digital-to-analog converter DAC.
On the other hand, FIG. 25 is a block diagram showing another example of the circuit arrangement of the conventional current-steering (current addition) digital-to-analog converter DAC. In this example, the digital-to-analog converter DAC includes N current-switching cells CS0, CS1, CS2, . . . , and CSN-1, as in FIG. 24. However, the N currents obtained by binary-weighting a current value are added using a single load resistor in accordance with the digital input signal bits of an N-bit binary code and thus converted into the analog output signal Vout and output.
That is, the digital-to-analog converter in FIG. 25 includes N D flip-flops D-FF which temporarily latch the N digital input signal bits D0 (LSB side), D1, D2, . . . , and DN-1 (MSB side) and output the signal bits retimed by the clock signal CLK, respectively, N current sources which flow N currents binary-weighted to current values I (LSB side), 2I, 22I, . . . , and 2N-1I (MSB side) to the single load resistor having the resistance value R, and switches S0, S1, S2, . . . , and SN-1 to be on/off-controlled based on the values of the digital input signal bits D0, D1, D2, . . . , and DN-1, respectively. Note that symbol VCC denotes the power supply configured to drive the digital-to-analog converter DAC.
Each of the conventional current-steering (current addition) digital-to-analog converters DACs shown in FIGS. 24 and 25 includes the N current-switching cells CS0, CS1, CS2, . . . , and CSN-1, as described above. In accordance with the digital input signal bits D0, D1, D2, . . . , and DN-1 of an N-bit binary code, the switches S0, S1, S2, . . . , and SN-1 corresponding to them are simultaneously driven (on/off) to change the weight of the current flowing to the load formed from the resistor ladder network or the single load resistor, that is, generate binary-weighted currents, thereby obtaining the analog output signal (voltage). In general, to make the driving timings of the switches S0, S1, S2, . . . , and SN-1 coincide, the N D flip-flops D-FF (circuits having a latch function) are arranged at the preceding stages of the switches S0, S1, S2, . . . , and SN-1, respectively. The digital-to-analog converter is configured to simultaneously drive the switches S0, S1, S2, . . . , and SN-1 by retiming the N digital input signal bits D0, D1, and DN-1 based on the same clock signal CLK.
The outline of the operations of the conventional current-steering (current addition) digital-to-analog converters DACs shown in FIGS. 24 and 25 will be described with reference to FIGS. 26A, 26B, and 27 by taking the digital-to-analog converter DAC in FIG. 25 as an example.
FIGS. 26A and 26B are schematic views for explaining the operation of a current-switching cell included in the conventional current-steering (current addition) digital-to-analog converter DAC. In particular, FIG. 26A shows the circuit arrangement of an Mth current-switching cell CSM of the N current-switching cells CS0, CS1, CS2, . . . , and CSN-1. FIG. 26B shows the signal waveforms of various parts of the Mth current-switching cell CSM shown in FIG. 26A. Note that FIG. 26A shows, as an example, a case in which a load resistor network (resistor ladder network) including a plurality of resistors formed in a ladder with resistance values R and 2R, as shown in FIG. 24, is provided as the load connected to the current-switching cell CSM.
The current-switching cell is a circuit (cell) which has a function of latching and retiming a digital input signal and a switch function of controlling whether to supply a current to the load side and is arranged in correspondence with a digital input signal bit. The current-switching cell includes a D flip-flop, a switch circuit, and a current source. This circuit controls whether to flow the current from the current source to the load by switching the on/off state of the switch circuit in accordance with the digital input signal latched and retimed by the D flip-flop.
An Mth digital input signal bit DM input to an Mth D flip-flop D-FFM, as shown in FIG. 26A, has a signal waveform as shown in FIG. 26B. The digital input signal bit is temporarily latched and retimed by the Mth D flip-flop D-FFM in accordance with a rising edge (timing indicated by Δ) of the clock signal CLK, as shown in FIG. 26B, and output to a switch SM as a retimed digital input signal DMR.
The digital signal DMR retimed to be coincident with the rising edge of the clock signal CLK drives the switch SM that is the switch circuit of the Mth current-switching cell CSM so as to determine whether to flow a current signal IM to the load resistor network (resistor ladder network). That is, as shown in FIG. 26B, when the retimed digital signal DMR is “High”, the switch SM is turned on to flow the current signal from the current source to the load resistor network.
The D/A (Digital-to-Analog) conversion operation of a digital-to-analog converter DAC including current-switching cells as described with reference to FIG. 26A will be described using FIG. 27, FIG. 27 is a schematic view for explaining the operation of the entire conventional current-steering (current addition) digital-to-analog converter DAC by taking a 3-bit structure as an example. FIG. 27 indicates that the analog output signal Vout corresponding to three digital input signal bits D0 (LSB side), D1, and D2 (MSB side) is generated.
Note that three current-switching cells CS0, CS1, and CS2 including D flip-flops D-FF0, D-FF1, and D-FF2, switch circuits, and current sources are provided in correspondence with the three digital input signal bits D0, D1, and D2, although not illustrated in FIG. 27. FIG. 27 illustrates the D flip-flops D-FF0, D-FF1, and D-FF2 but shows the remaining switch circuits and the current sources of the current-switching cells CS0, CS1, and CS2 in a form different from FIG. 24 or 25 as a DAC core circuit 100 that performs the D/A conversion operation together with the load-side resistor ladder network.
Referring to FIG. 27, the digital input signal bits D0, D1, and D2 are input to the digital-to-analog converter DAC. The three digital input signal bits D0, D1, and D2 are external signal bits. In general, the three data bits somewhat have a shift on the time axis, as shown in FIG. 27.
Each of the three digital input signal bits D0, D1, and D2 is input to a corresponding one of the D flip-flops D-FF0, D-FF1, and D-FF2, latched, retimed to a rising edge (timing indicated by Δ) of the external clock signal CLK to eliminate the shift on the time axis, and output as a corresponding one of retimed digital input signals D0R (LSB side), D1R, and D2R (MSB side).
After that, the retimed digital input signals D0R, D1R, and D2R simultaneously drive the switches S0, S1, and S2 of the switch circuits provided in the DAC core circuit 100 to flow the currents from the current sources to the load (the load resistor network in the example shown in FIG. 26A). The currents are thus weighted in accordance with the values of the retimed digital input signal bits D0R, D1R, and D2R. Finally, the analog output signal Vout (voltage) in eight levels (=23) corresponding to the digital input signal bits D0, D1 and D2 is generated and output, as shown in FIG. 27.
An interleaving method is a technique of increasing the conversion speed of the digital-to-analog converter DAC, which is explained in, for example, non-patent reference 3: C. Frail et al, “Time-Interleaved Digital-to-Analog Converters for UWB Signal Generation” contained in the proceedings of IEEE International Conference on Ultra-Wideband 2007. FIG. 28 is a block diagram showing an example of the arrangement of a conventional interleaved digital-to-analog converter DAC described in non-patent reference 3. As a sub-digital-to-analog converter SDAC that performs the interleaving operation, two digital-to-analog converters DACs having the same conversion speed performance are provided.
The digital-to-analog converter DAC having the circuit arrangement as shown in FIG. 28 includes a first sub-digital-to-analog converter (SDAC1) 101, a second sub-digital-to-analog converter (SDAC2) 102, a clock (CLK) 103, a first phase shifter 104, a second phase shifter 105, and a mixer 106.
In the digital-to-analog converter DAC having the circuit arrangement as shown in FIG. 28, the first phase shifter 104 and the second phase shifter 105 generate clock signals of different phases based on the clock signal from the clock (CLK) 103. The first sub-digital-to-analog converter (SDAC1) 101 and the second sub-digital-to-analog converter (SDAC2) 102, which have the same conversion speed performance, thus perform the interleaving operation.
The mixer 106 combines the analog output signals output from the first sub-digital-to-analog converter (SDAC1) 101 and the second sub-digital-to-analog converter (SDAC2) 102. This enables to generate an analog output signal corresponding to twice the conversion speed of each of the first sub-digital-to-analog converter (SDAC1) 101 and the second sub-digital-to-analog converter (SDAC2) 102.
For example, assume that each of the first sub-digital-to-analog converter (SDAC1) 101 and the second sub-digital-to-analog converter (SDAC2) 102 can operate at a conversion speed of 14 GS/s. In this case, when the interleaving method of causing the first sub-digital-to-analog converter (SDAC1) 101 and the second sub-digital-to-analog converter (SDAC2) 102 to perform the interleaving operation, an analog output signal corresponding to 28 GS/s can be obtained.